1. Field of the Invention
The present invention relates to a semiconductor read only memory, and more particularly to a semiconductor read only memory in which MOSFETs (metal-oxide-semiconductor field effect transistors) constituting memory cells are connected in parallel.
2. Description of the Related Art
FIG. 5 shows an equivalent circuit of a semiconductor read only memory (hereinafter, referred to as "ROM") which is conventionally and widely used. The ROM in FIG. 5 is a lateral ROM including a plurality of word lines 1, a plurality of bit lines 2 which cross the word lines 1 and memory cells 3 each constituted by a MOSFET. Each memory cell 3 is connected in parallel between two adjacent bit lines 2. It is known that each of the bit lines 2 is a diffusion bit line formed of a diffusion layer or a metal bit line formed of a metal.
Further, for example in Japanese Patent Application No. 3-77914 (corresponding to the related, commonly assigned U.S. application Ser. No. 07/845,257, filed Mar. 3, 1992, naming Y. Hotta as inventor entitled "Semiconductor Read Only Memory" and now U.S. Pat. No. 5,268,861), in order to dispose memory cells more densely, a hierarchical bit line system including main bit lines and sub-bit lines has been proposed for the ROM.
FIG. 6 shows a circuit diagram showing park of a ROM using the hierarchical bit line system. In the hierarchical bit line system, each of main bit lines such as MB.sub.1 is disposed between two adjacent sub-bit lines, namely, an odd-numbered sub-bit line such as SB.sub.1 and an even-numbered sub-bit line such as SB.sub.2. Each of the memory cells M.sub.ij constituted by MOSFETs is connected between such two adjacent sub-bit lines. The two adjacent sub-bit lines function as a source and a drain, respectively, for each of the memory cells M.sub.ij. Further, gates of the memory cells M.sub.ij are connected to a word line WL.sub.j.
The main bit lines MB.sub.1, MB.sub.2, . . . , etc. are connected to sense amplifiers SA.sub.1, SA.sub.3, . . . , etc. or grounded via transistors Q.sub.2, Q.sub.4, . . . , etc. Here, the odd-numbered main bit lines are each connected to a sense amplifier, and the even-numbered main bit lines are each grounded. Ends of the odd-numbered sub-bit lines such as SB.sub.1 on the side of the memory cells M.sub.i1 (i.e., on the upper side in FIG. 6 ) are connected to bank selecting MOSFETs BSO.sub.m, respectively. Two adjacent bank selecting MOSFETs, for example, BSO.sub.1 and BSO.sub.2 are also connected to the odd-numbered main bit line MB.sub.1 disposed therebetween. Further, a gate of each of the odd-numbered bank selecting MOSFETs BSO.sub.1, BSO.sub.3, . . . , etc. is connected to a bank selecting line BO.sub.1, and a gate of each of the even-numbered bank selecting MOSFETs BSO.sub.2, BSO.sub.4, . . . , etc. is connected to a bank selecting line BO.sub.2.
Further, ends of the even-numbered sub-bit lines such as SB.sub.2 on the side of the memory cells M.sub.ij (i.e., on the lower side in FIG. 6) are connected to bank selecting MOSFETs BSE.sub.m, respectively. Two adjacent bank selecting MOSFETs, for example, BSE.sub.1 and BSE.sub.2 are also connected to the even-numbered main bit line MB.sub.2 disposed therebetween. Further, a gate of each of the odd-numbered bank selecting MOSFETs BSE.sub.1, BSE.sub.3, . . . , etc. is connected to a bank selecting line BE.sub.1, and a gate of each of the even-numbered bank selecting MOSFETs BSE.sub.2, BSE.sub.4, . . . , etc. is connected to a bank selecting line BE.sub.2.
FIG. 7 shows a pattern on a surface of a semiconductor substrate in the case where diffusion bit lines are used as the sub-bit lines in the circuit shown in FIG. 6.
In the ROM with the hierarchical bit line system shown in FIG. 6, the wiring pitch of the main bit lines can be made double as compared with that of the conventional lateral ROM shown in FIG. 5 . Accordingly, the ROM with the hierarchical bit line system has an advantage of reducing the parasitic capacitance of bit lines.
Moreover, in the case where the diffusion bit lines are used in the ROM with the hierarchical bit line system shown in FIG. 6, the wiring resistance can be greatly reduced. Therefore, the resistance to a discharge current for reading out information from each memory cell can be uniform regardless of positions of the memory cells from which information is read out.
However, in the ROM shown in FIG. 6, since the bank selecting MOSFETs are connected to the memory cells in series, the discharge current for reading out information from each memory cell greatly depends on a driving current for the bank selecting MOSFET connected thereto. Accordingly, in order to realize a high-speed reading operation, the discharge current should be increased by enlarging areas where the bank selecting MOSFETs are provided. Such an enlargement increases the chip size.
In the ROM shown in FIG. 6, information is read out, for example, from a memory cell M.sub.41 in the following manner. In this case, the bank selecting lines BO.sub.1 and BE.sub.2 are set to be High, the bank selecting lines BO.sub.2 and BE.sub.1 are set to be Low, and the word line WL.sub.1 is set to be High. In addition, a control signal VG.sub.1 for the transistor Q.sub.2 connected to the main bit line MB.sub.2 is set to be High, so that the main bit line MB.sub.2 is grounded.
FIG. 4 schematically shows a discharge current flow for reading out information from the memory cell M.sub.41. The discharge current flows through the main bit line MB.sub.3, the bank selecting MOSFET BSO.sub.3, the sub-bit line SB.sub.5, the memory cell M.sub.41, the sub-bit line SB.sub.4, the bank selecting MOSFET BSE.sub.2, and the main bit line MB.sub.2, in this order. Due to such a current flow in the circuit, the discharge current greatly depends on the driving current for the two bank selecting MOSFETs BSO.sub.3 and BSE.sub.2 both connected to the memory cell M.sub.41 in series. If the driving currents for the bank selecting MOSFETs BSO.sub.3 and BSE.sub.2 are increased, the discharge current can be increased. When areas where the bank selecting MOSFETs are provided are enlarged so as to increase the driving currents for the bank selecting MOSFETs, however, there arises a problem that the chip size is enlarged.